Edge AI hardware faces a hard limit. Running deep neural networks on battery-powered devices requires massive computational throughput within a strict power budget. Traditional digital processors, including GPUs, TPUs, and specialized digital NPUs, spend most of their energy moving data rather than computing. To understand how standard architectures handle these transfers, see how GPUs process memory reads at the hardware level. Moving weights from memory arrays to processing units consumes orders of magnitude more power than the actual multiplication and addition. This energy cost is known as the memory wall.
Mythic addresses this bottleneck by replacing digital logic with analog compute-in-memory (CIM) architecture. This represents a broader industry shift toward application-specific hardware, similar to etching models in silicon to bypass general-purpose GPU limitations. Instead of fetching weights from memory to feed arithmetic logic units (ALUs), the computation occurs directly inside the memory array. This design uses mature flash memory technology to perform vector-matrix multiplication at a fraction of the power required by digital alternatives.
The Physics of Analog Matrix Multiplication
At the core of the architecture lies a simple application of basic electrical laws. Digital processors represent numbers as binary states, switching transistors on and off to perform arithmetic. Mythic's chip represents weights as variable analog conductance values within modified flash memory cells.
To perform vector-matrix multiplication, the architecture utilizes Ohm's Law and Kirchhoff's Current Law. When an input vector is applied to the memory array, it is converted into analog voltages. These voltages are applied to the rows of the flash memory grid.
Each flash cell at the intersection of a row and column acts as a resistor with a programmed conductance. According to Ohm's Law, the current flowing through a cell is the product of the input voltage and the cell conductance:
I = V \cdot G
Here, V represents the input activation, and G represents the weight stored as conductance. As currents from each cell in a column flow down to the output line, they sum together naturally. This summation follows Kirchhoff's Current Law:
I_{total} = \sum (V_i \cdot G_i)
The total current at the bottom of the column represents the dot product of the input vector and the weight vector stored in that column. An entire matrix multiplication occurs in a single step, using the physical properties of the silicon rather than clock-driven digital logic gates.
Flash Memory as a Computing Element
Using flash memory for analog computing requires precise control over the charge stored on the floating gate of each transistor. Standard digital flash memory only needs to distinguish between two states (single-level cell) or a few states (multi-level cell). Mythic programs the floating gates to hold one of up to 256 distinct charge levels, representing an 8-bit weight value.
Programming these cells to precise analog values requires iterative pulsing algorithms. The hardware applies short programming pulses to inject or remove electrons from the floating gate, measuring the resulting conductance between pulses until the target value is reached. Once programmed, the weights are non-volatile. They remain in the array without drawing leakage current, eliminating the standby power consumption that plagues SRAM-based systems.
Standard NOR flash arrays serve as the physical foundation. NOR flash allows random access to individual cells, making it suitable for mapping arbitrary neural network weight matrices. The high density of flash allows millions of weights to fit into a small silicon area, lowering production costs compared to chips built on advanced, expensive digital process nodes.
Inside the M1076 Analog Matrix Processor
The M1076 Analog Matrix Processor (AMP) implements this technology across a scalable tile-based architecture. The chip contains 76 individual tiles connected by a high-bandwidth digital network-on-chip (NoC). Each tile operates as an independent computing unit containing both analog and digital components.
Inside a single tile, you find:
- A large analog compute engine containing the flash memory arrays.
- Digital-to-analog converters (DACs) to translate incoming digital activations into analog voltages.
- Analog-to-digital converters (ADCs) to convert the resulting column currents back into digital values.
- A local digital SIMD (Single Instruction, Multiple Data) vector engine.
- Local SRAM for storing intermediate activations and bias values.
- A router to manage data transfer across the NoC.
The hybrid design is necessary because neural networks require operations beyond matrix multiplication. While the analog engine handles the heavy linear projections, the digital SIMD engine executes non-linear activation functions like ReLU, Sigmoid, or GeLU, along with pooling, batch normalization, and element-wise additions.
This division of labor keeps the control flow digital and flexible. The digital components handle routing, scheduling, and activation processing, while the analog cores run the power-hungry matrix math.
Managing Noise and Environmental Drift
Analog computation introduces challenges that do not exist in the deterministic digital domain. Temperature fluctuations, voltage supply noise, and manufacturing variations can alter the conductance of flash cells or change the behavior of the DACs and ADCs. Without mitigation, these variations degrade the accuracy of neural networks.
Mythic uses several hardware and software strategies to counter these effects. On the hardware level, the chip includes reference cells and calibration circuits that dynamically measure and compensate for temperature drift. The ADCs use adaptive calibration to correct for offset and gain errors in real-time.
On the software level, the compiler plays a major role. Standard neural networks trained in 32-bit floating-point precision cannot be directly deployed onto analog hardware. The compiler uses quantization-aware training (QAT) to simulate the noise, quantization limits, and non-linearities of the analog hardware during the training process.
By exposing the network to these hardware constraints during training, the weights adjust to be resilient to minor analog variations. The resulting models achieve inference accuracy comparable to digital INT8 implementations, even when running on noisy analog silicon.
SRAM vs. Flash in Compute-in-Memory Architectures
Other hardware designers have explored compute-in-memory using SRAM or emerging non-volatile memories like ReRAM and Phase Change Memory (PCM). Comparing these technologies reveals why flash is a pragmatic choice for immediate deployment.
SRAM-based CIM architectures offer high speed and endurance, but they suffer from high leakage current. SRAM cells must be powered continuously to retain their state. If the system goes idle, it still draws power. Additionally, SRAM cells are physically large, requiring six transistors per bit, which limits the density of weights you can pack onto a single chip.
ReRAM and PCM offer high density and non-volatility, but the manufacturing processes for these materials are still maturing. They suffer from high write-endurance degradation and device-to-device variability.
Flash memory uses standard, mature CMOS fabrication processes. The semiconductor industry has spent decades optimizing flash manufacturing, resulting in high yields, predictable reliability, and low costs. Using flash allows Mythic to build chips on mature process nodes like 40nm or 28nm while still outperforming digital chips fabricated on expensive 7nm or 5nm nodes.
Software Compilation and Mapping
Deploying a model to the M1076 processor requires translating a standard machine learning graph (such as an ONNX or PyTorch model) into a physical hardware configuration. The Mythic compiler automates this process through several stages.
First, the compiler analyzes the model graph and partitions the weight matrices. If a layer is too large to fit into a single tile's flash array, the compiler splits the matrix across multiple tiles. The network-on-chip is programmed to route the intermediate outputs from one tile to the next, forming a pipelined execution path.
Second, the compiler schedules the execution sequence. Because the weights are stored permanently in the flash arrays, there is no overhead for loading weights during execution. The compiler configures the tiles to stream activation data through the mapped network layers.
Finally, the compilation toolchain performs calibration. It runs representative input data through a simulator to determine the optimal dynamic range for the DACs and ADCs at each layer, maximizing the signal-to-noise ratio during runtime.
Performance, Power, and Target Use Cases
The M1076 AMP delivers up to 25 TOPS of AI performance while drawing approximately 3 to 4 watts of power. This efficiency profile translates to roughly 6 to 8 TOPS per watt, which is significantly higher than comparable digital edge processors.
This efficiency is valuable for edge devices where power budgets are constrained by thermal limits or battery capacity. Target applications include:
- Video surveillance: Running multi-channel object detection, tracking, and classification on edge gateways.
- Drones and robotics: Processing high-frame-rate camera feeds for navigation and obstacle avoidance without draining the propulsion battery.
- Industrial automation: Monitoring high-speed sensor streams for anomaly detection directly on the factory floor.
- Defense and aerospace: Processing sensor data in remote environments where power generation is limited.
By running inference locally at low power, devices do not need to upload constant video streams to the cloud. This reduces bandwidth costs, lowers latency, and improves privacy. For cloud-based alternatives that protect sensitive data, developers use homomorphic encryption for private AI inference.
The Future of Analog Compute
Digital processors are reaching the limits of dimensional scaling. As transistors stop shrinking at historical rates, architectural changes are required to sustain performance gains. Analog compute-in-memory represents a departure from the traditional Von Neumann architecture that has dominated computing for decades.
While digital processors will remain necessary for general-purpose computing and high-precision tasks, analog accelerators offer a viable path forward for specialized, high-throughput workloads like deep learning inference. By utilizing the physical properties of silicon to perform mathematics, architectures like Mythic's demonstrate that efficiency gains can be achieved through clever physics rather than raw transistor scaling.
